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In article <51f8562a.0411090425.71cff2f7@posting.google.com>
download-ein-trojaner-virus-und-es-gibt@meine-wahrheit-deine-wahrheit.de (http://tinyurl.com/6r9ez) wrote:
download-ein-trojaner-virus-und-es-gibt@meine-wahrheit-deine-wahrheit.de (http://tinyurl.com/6r9ez) wrote:
Boring.
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In article <51f8562a.0411110343.2520f66b@posting.google.com>
download-ein-trojaner-virus-und-es-gibt@meine-wahrheit-deine-wahrheit.de (http://tinyurl.com/6r9ez) wrote:
download-ein-trojaner-virus-und-es-gibt@meine-wahrheit-deine-wahrheit.de (http://tinyurl.com/6r9ez) wrote:
Boring.
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In article <51f8562a.0411120329.2a154387@posting.google.com>
download-ein-trojaner-virus-und-es-gibt@meine-wahrheit-deine-wahrheit.de (http://tinyurl.com/6r9ez) wrote:
download-ein-trojaner-virus-und-es-gibt@meine-wahrheit-deine-wahrheit.de (http://tinyurl.com/6r9ez) wrote:
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davidjames@mj.shawcable.net wrote:
C
cfk
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Dear John:
One way to accomplish this task is to use a schematic editor that
outputs a netlist in a format consistent with a toolflow that eventually
gets you to an FPGA.
Many of the tools, including WebPack do this. You can design a schematic
and output as its netlist format, verilog, vhdl, edif or others.
But, I suspect your question is really deeper then this.
I was at a similar point a while back. I have studied several tool sets
over the last year including WebPack, ISE, Synopsys, LEDIT, Icarus,
Modeltech, XCircuit, Magic, LASI, ICFB and others. It may very well be that
the real question you are asking is how do the various tools flow together
in order to allow me to express my ideas in a way that can be realized in an
FPGA or ASIC.
There are many answers to that question. Personally, I find the answer
seems to be one of jumping into the tools with a vigor and figuring out what
they do. If I dont do this, then I spend virtually *all of my time* arguing
whether:WebPAck vs ISE, ISE vs Synopsys, Orcad as schematic editor, Icarus
vs Synplicity, Cadence vs Mentor, (Linux vs windows)
All of which is a waste of time.
So, just pick a path an go. It doesnt really matter which path you pick. But
when you pick a path, let us know and we can help guide you a bit.
Charles
"John K." <INVALIDANTISPAM@aol.com> wrote in message
news:bj9sb2$gc4bj$3@ID-50260.news.uni-berlin.de...
One way to accomplish this task is to use a schematic editor that
outputs a netlist in a format consistent with a toolflow that eventually
gets you to an FPGA.
Many of the tools, including WebPack do this. You can design a schematic
and output as its netlist format, verilog, vhdl, edif or others.
But, I suspect your question is really deeper then this.
I was at a similar point a while back. I have studied several tool sets
over the last year including WebPack, ISE, Synopsys, LEDIT, Icarus,
Modeltech, XCircuit, Magic, LASI, ICFB and others. It may very well be that
the real question you are asking is how do the various tools flow together
in order to allow me to express my ideas in a way that can be realized in an
FPGA or ASIC.
There are many answers to that question. Personally, I find the answer
seems to be one of jumping into the tools with a vigor and figuring out what
they do. If I dont do this, then I spend virtually *all of my time* arguing
whether:WebPAck vs ISE, ISE vs Synopsys, Orcad as schematic editor, Icarus
vs Synplicity, Cadence vs Mentor, (Linux vs windows)
All of which is a waste of time.
So, just pick a path an go. It doesnt really matter which path you pick. But
when you pick a path, let us know and we can help guide you a bit.
Charles
"John K." <INVALIDANTISPAM@aol.com> wrote in message
news:bj9sb2$gc4bj$3@ID-50260.news.uni-berlin.de...
J
John K.
Guest
Hi David Brown (david@no.westcontrol.spam.com), you wrote:
more difficult to use schematic than HDL as projects get larger.
I think in a "object oriented" way.. for example, I make Flip-Flops from
NAND gates. So I get a Flip-Flop object. I make registers/latches from
Flip-Flops, so I get a Latch object. I mean, complexity can naturally
get encapsulated and encapsulated, till you have a whole ALU, or a whole
processor, etc.. and your schematic always looks simple (circuits and
subcircuits encapsulated into virtual devices).
I don't have much experience with current schematic software (I used
mostly my own.. nothing fancy anyway, but worked well for encapsulating
at least), but I see no reason why schematic based (using macros) should
be any slower or more confusing than HDLs?
I can only think about one problem: simulation gets slower and slower.
But neither this must be true: if simulating a whole Latch via NAND
gates may be slow, after I know it works well and I have its timing
characteristics known, I can encapsulate also them into the "black
box" and simulation of a Latch will be very quick.. having just to
simulate the function (and delays) from input to output.
HDL's IMHO are very confusing, hardware wise. A schematic is much more
natural and intuitive. IMHO of course.
On the other hand the non-intuitive, too abstract HDLs will make you
design things that then in silicon are very inefficient.. will not
give you a good "big, real picture" of what you're doing, etc..
schematic idea per se, but in the current software.
This is a typical situation for the usual "no programs satisfied my needs,
so I wrote my own".
Too bad I don't have that much free time.. so I'd prefer to stick with
something already available. I have my own schematic based simulator but
its editor is nothing mature at all, and it's missing many features.
I can't help.. it's a hobbyst project and I have to enjoy it. This definitely
means "no HDLs".
You mean that I could do schematic entry and schematic simulation on any
software that is able to save in EDIF format? What would be the best software
(simulation-wise) capable of it, can you name a few?
And then I could load the EDIF file into Webpack (?) and from there what
should I do? Is further simulation (more FPGA-device targetted) possible?
How could I express things like block-ram in the former schematic program,
if it's quite totally separed from the back-end tools?
Thanks for your time!
John
I always liked reasoned arguements.. go ahead.
I'm not saying you're wrong, but I don't understand what makes inherently
more difficult to use schematic than HDL as projects get larger.
I think in a "object oriented" way.. for example, I make Flip-Flops from
NAND gates. So I get a Flip-Flop object. I make registers/latches from
Flip-Flops, so I get a Latch object. I mean, complexity can naturally
get encapsulated and encapsulated, till you have a whole ALU, or a whole
processor, etc.. and your schematic always looks simple (circuits and
subcircuits encapsulated into virtual devices).
I don't have much experience with current schematic software (I used
mostly my own.. nothing fancy anyway, but worked well for encapsulating
at least), but I see no reason why schematic based (using macros) should
be any slower or more confusing than HDLs?
I can only think about one problem: simulation gets slower and slower.
But neither this must be true: if simulating a whole Latch via NAND
gates may be slow, after I know it works well and I have its timing
characteristics known, I can encapsulate also them into the "black
box" and simulation of a Latch will be very quick.. having just to
simulate the function (and delays) from input to output.
HDL's IMHO are very confusing, hardware wise. A schematic is much more
natural and intuitive. IMHO of course.
On the other hand the non-intuitive, too abstract HDLs will make you
design things that then in silicon are very inefficient.. will not
give you a good "big, real picture" of what you're doing, etc..
Yep, and that just makes me think that the problem is not in the
schematic idea per se, but in the current software.
This is a typical situation for the usual "no programs satisfied my needs,
so I wrote my own".
Too bad I don't have that much free time.. so I'd prefer to stick with
something already available. I have my own schematic based simulator but
its editor is nothing mature at all, and it's missing many features.
Right, I feel much "out of the world" by not following the HDL route.. but
I can't help.. it's a hobbyst project and I have to enjoy it. This definitely
means "no HDLs".
That's very interesting. Please, can you elaborate more on this?
You mean that I could do schematic entry and schematic simulation on any
software that is able to save in EDIF format? What would be the best software
(simulation-wise) capable of it, can you name a few?
And then I could load the EDIF file into Webpack (?) and from there what
should I do? Is further simulation (more FPGA-device targetted) possible?
How could I express things like block-ram in the former schematic program,
if it's quite totally separed from the back-end tools?
Thanks for your time!
John
J
John K.
Guest
Hi Alex Gibson (alxx@ihug.com.au), you wrote:
I can't find any schematic option in the New Source window.
I can see only:
User Document
BMM File
MEM File
Implementation Constraints File
it's very confusing for me to find the right target device. What
would be a rough equivalent of the Spartan 2E 300? Altera has so
many families that it's very confusing (at least for me).
Moreover, what about programmers and development boards? My former
choice for Xilinx was motivated by the large (till 10 millions of
equivalent (fake, I know) gates!) rich choice of sizes, the low
cost development boards (like the ones from Digilent and Burched)
with integrated programmer. I need cheap, for the moment.
One thing, though, that puzzled me is why similar designs to the
one I have in mind, i.e. the C-One and XGameStation, both use
Altera devices. No, I won't ask if they're superior than Xilinx
(or inferior, for the matter ) to avoid to cause a possible
very boring flamewar here.
What I really ask is instead if Altera devices are suitable for
low budget development (just to get confident with the FPGA world)
using schematic entry and simulation, and if then they will offer
the power to do serious stuff, without having to dump it all and
change brand/family of chips. Moreover, why not Actel or Lattice/
Vantis, or why not Lucent or QuickLogic (just to name those that
I heard the existance of and visited thousands times the website
of, without much results anyway)?
Moreover, if I go with Altera, which are the families roughly
equivalent in specs to the Spartan 2E and Virtex of Xilinx?
Thanks a lot for all your big patience and help!
Greets,
John
Maybe it's because I'm using the v5.2.03i of the free WebPack, but
I can't find any schematic option in the New Source window.
I can see only:
User Document
BMM File
MEM File
Implementation Constraints File
Yup, I'm thinking to dump Xilinx and go with Altera instead. But
it's very confusing for me to find the right target device. What
would be a rough equivalent of the Spartan 2E 300? Altera has so
many families that it's very confusing (at least for me).
Moreover, what about programmers and development boards? My former
choice for Xilinx was motivated by the large (till 10 millions of
equivalent (fake, I know) gates!) rich choice of sizes, the low
cost development boards (like the ones from Digilent and Burched)
with integrated programmer. I need cheap, for the moment.
One thing, though, that puzzled me is why similar designs to the
one I have in mind, i.e. the C-One and XGameStation, both use
Altera devices. No, I won't ask if they're superior than Xilinx
(or inferior, for the matter
) to avoid to cause a possiblevery boring flamewar here.
What I really ask is instead if Altera devices are suitable for
low budget development (just to get confident with the FPGA world)
using schematic entry and simulation, and if then they will offer
the power to do serious stuff, without having to dump it all and
change brand/family of chips. Moreover, why not Actel or Lattice/
Vantis, or why not Lucent or QuickLogic (just to name those that
I heard the existance of and visited thousands times the website
of, without much results anyway)?
Moreover, if I go with Altera, which are the families roughly
equivalent in specs to the Spartan 2E and Virtex of Xilinx?
Thanks a lot for all your big patience and help!
Greets,
John
T
Todd H.
Guest
NOSPAM@invalid.com (Michael) writes:
CPU's being build from gates. I believe they're designed full custom
at the transistor level because density is way too important.
You need at least 4 transistors to make an SRAM cell, plus 2 more
thingees--be they resistive pull-ups or thin film transistors for the
pull-up load.
Best Regards,
--
Todd H.
http://www.toddh.net/
I highly doubt that you'll find the SRAM macros tha go into modern
CPU's being build from gates. I believe they're designed full custom
at the transistor level because density is way too important.
You need at least 4 transistors to make an SRAM cell, plus 2 more
thingees--be they resistive pull-ups or thin film transistors for the
pull-up load.
Best Regards,
--
Todd H.
http://www.toddh.net/
M
Mike Seningen
Guest
Cache needs some sort of tag to know what line in memory it is
referencing. SRAM is the memory location itself.
Other than that -- the two can be identical.
m.
Michael wrote:
referencing. SRAM is the memory location itself.
Other than that -- the two can be identical.
m.
Michael wrote:
T
Todd H.
Guest
NOSPAM@invalid.com (Michael) writes:
of SRAM cells after all..plus supporting logic for the tag and
matching logic, so you can expect the overall transistor density to be
lower on a cache than plain SRAM "field" that doesn't have the metal
interconnect that the logic gates would.
don't know what sort of SRAM cell the 486 used for its L1 cache. I'd
be shocked if the sram cells were made of logic gates, though, I can
say that.
devices, or using 6 (4 n, 2 p) transistors in CMOS, or using 4 n
transistors and 2 thin film transistors for the the pull-up load. Or
I suppose you could easily do one with gates, but if you need a lot of
them, the geometric economy goes to crap because you end up with some
big assed cells.
I believe most CPU's and MCU's use an SRAM cache "macro" in their
layout...which means the SRAM portion for the caches is custom
designed (probably still at the transistor level, I'd have to think)
and laid out in a modular way so that they can be plopped into the
layout of a CPU. Memory design specialists design the macro and CPU
architects and layout designers drop the macro onto the chip layout
and hook it up from there.
Best Regards,
--
Todd H.
http://www.toddh.net/
All depends on the layout and the technology. L1 cache is made up
of SRAM cells after all..plus supporting logic for the tag and
matching logic, so you can expect the overall transistor density to be
lower on a cache than plain SRAM "field" that doesn't have the metal
interconnect that the logic gates would.
I was a standalone full-custom SRAM chip designer7, so I'm afraid I
don't know what sort of SRAM cell the 486 used for its L1 cache. I'd
be shocked if the sram cells were made of logic gates, though, I can
say that.
Basic SRAM cells can be made of 4 transitors with 2 resistive pull up
devices, or using 6 (4 n, 2 p) transistors in CMOS, or using 4 n
transistors and 2 thin film transistors for the the pull-up load. Or
I suppose you could easily do one with gates, but if you need a lot of
them, the geometric economy goes to crap because you end up with some
big assed cells.
I believe most CPU's and MCU's use an SRAM cache "macro" in their
layout...which means the SRAM portion for the caches is custom
designed (probably still at the transistor level, I'd have to think)
and laid out in a modular way so that they can be plopped into the
layout of a CPU. Memory design specialists design the macro and CPU
architects and layout designers drop the macro onto the chip layout
and hook it up from there.
Best Regards,
--
Todd H.
http://www.toddh.net/
C
chad
Guest
And <fourthrounds@toontoon.com> wrote in news:cbiahr$303c$678
@news.nextra.cz:
@news.nextra.cz:
I'm sure RedDog would love to!
Though I think he really has a thing for Apu.
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